Phone: (209) 222-8685
I am a self-driven veteran of the ASIC/FPGA AND IC design in the tech industry, with over 20 years of experience across all technical disciplines of chip/ASIC or IC design as well as FPGA design, extensive hands-on experience as well as managing cross-functional international teams through all aspects of the chip design through production. I have a proven track record of successful, time-crunched seemingly "impossible" tape-outs of flagship products. When I’m not doing chips, I hack computer vision and deep learning to fit on platforms such as Raspberry-Pi.
I am also an Expert Witness for cases that involve semiconductor devices, mobile devices, GPS, electronic design automation (EDA), hardware, chips, IC Design, ASIC Design, SoC Design or FPGA design, as well as software, and embedded firmware.
Expert Witness in patent and liability cases that involve semiconductor devices, mobile devices, GPS, electronic design automation (EDA), hardware, chips, IC Design, ASIC Design, SoC Design or FPGA design, as well as software, and embedded firmware.
Extensive IP (Intellectual Property) experience
patent development, analysis, licensing, and strategic positioning. Holds 4 US patents.
Architecture and RTL Design and verification
hands-on experience with architectures of many SoCs and complex blocks as well as RTL writing and functional verification for both ASIC and FPGA. Extreme knowledge in design for PPA, i.e. architecting an SoC to meet timing, power and area budgets from the get-go, making the rest of the flow almost a push button.
From whitepapers to publications, I am consistently writing and teaching my craft to others
Extensive hands-on experience with the following tools
SoC architecture design Verilog and RTL design, Functional Verification, physical synthesis, timing closure, place and route, DFT, extraction, clock tree synthesis, Perl scripting, Python, Git/CVS/Mercurial, Tcl, Timing constraints design, Running computer vision in real time on platforms like Raspberry Pi
Over 20 years of experience
in developing a range of product areas: networking, wireless/cellular communications, Switch ASICs CPUs, DSPs, FPGAs, software, firmware, system, IPs, CAD/SW tools.
Over 12 years of experience
in senior management of design and production of integrated circuits, FPGAs, SW, and CAD tools, from conception to mass-production.
Many successful unique complex, SoCs
brought from concept to volume production in multiple companies. Many more tape-outs, shrinks, and product derivatives were brought to production. Covering 65nm down to 10nm processes
EDA tools and IP
Responsible for all IP and EDA tools. Negotiated agreements for the purchase of EDA/CAD tools silicon, IP, other vendors, and known foundries for over $20M
Background & Expertise
2019 - Now
Helping my clients with patent and liability cases that involve semiconductor devices, mobile devices, GPS, electronic design automation (EDA), hardware, chips, IC Design, ASIC Design, SoC Design or FPGA design, as well as software, and embedded firmware.
Patent/IP Cases: Patent infringement and validity analysis. Code/hardware reviews
Product Liability Cases: Point of failure analysis - did a failure happen due to hardware, software. Analyze and identify the point of failure.
Participated in 14 hours of SEAK training on how to start and run an expert witness practice.
Founder & Managing Partner, AlephZero Consulting, LLC.
2017 - Now
AlephZero Consulting, LLC is a unique consultancy with extreme experience in designing complex algorithm design, chip/FPGA design as well as embedded (real-time) software/firmware design. Our customers range from chip design companies, automotive companies, automotive radar and lidar makers, retail automation companies, financial institutions and more.
Leading the hardware and embedded software/firmware design of our consultancy.
Hands-on chip design work for fabless semiconductor companies in the areas of Architecture, SoC Architecture, RTL Design, Verification, early power/area estimation, early floor planning and PPA calculations, flow optimizations, physical synthesis, P&R and timing closure.
Developed real-time image object detector using neural networks on a Raspberry Pi as an initial prototype and proof of concept for a customer
Perl and Python scripting for several customers as part of the overall help with prototyping and chip design
Director of VLSI, Rockley Photonics Inc.
2015 - 2017
Director of VLSI at Rockley Photonics, a well-funded start-up company that designs and manufactures opto-electrical switch ASICs for data centers. Responsible for the entire VLSI development in the company (digital and analog).
Managed the design of the company's flagship large and complex switch ASIC (~200mm sq), Topanga-1 - a 1.2TB throughput switch ASIC with in-house analog mixed-signal periphery to enable on-package optical/electrical integration
Built a fully functional digital and analog team from scratch.
Negotiated and put together many partner relationships that included direct access to TSMC (rare for a start-up) as well as design EDA tools, IP and services agreements with companies like Synopsys, Cadence, Mentor Graphics and other partners
Senior Director of VLSI Engineering, Mindspeed Technologies (acquired by Intel in 2014)
2011 - 2015
Managed all the projects/products of Intel's wireless cellular base-station products – overall 2 existing chip families and one next-generation family that's currently being designed.
Managed and hands-on participation in the development from the concept of T2200/T3300 devices, the company’s wireless small-base-station baseband processor flagship products.
Hands-on and management positions
Held hands-on engineering and management positions in companies such as Motorola Semiconductor, Intel, Broadcom, Agere/LSI, and a few successful startups
Interested in learning more about my professional background?
What I’ve Learned
Ben Gurion University, Israel
1995 - 1998
B.Sc. in Electrical and Computer Engineering
(Finished full curriculum of B.Sc EE, plus a few M.Sc. courses in 3 years instead of 4)
Senior IEEE member
Senior Member, IEEE Consultants Network
Senior Member, IEEE Circuits and Systems Society
Senior Member, IEEE Communications Society
Senior Member, IEEE Computational Intelligence Society
Senior Member, IEEE Consumer Electronics Society
Senior Member, IEEE Engineering in Medicine and Biology
Senior Member, IEEE Signal Processing Society
Senior Member, IEEE Systems, Man, and Cybernetics Society
Senior Member, IEEE Technology and Engineering Management Society
Senior Member, IEEE Systems Council
Senior Member, IEEE Council on Electronic Design Automation
”A methodology for timely verification of a complex SoC,” IEEE 2009 International SoC Design Conference (ISOCC), Busan, 2009, pp. 137-140.
"Reduction in ATE Test time for Core Wrapped (Border Sealed) blocks by Avoiding Q->SI at speed timing arcs & Interface X sources", Intel SoC Conference
Los Angeles, CA, USA